1. Field of the Invention
The present invention relates generally to a method for forming a magnetoresistance random access memory (MRAM), and more particularly to a method for forming magnetoresistance memory random access memory with a pseudo spin valve (PSV).
2. Description of the Prior Art
As semiconductor devices become highly integrated, the area occupied of the chip has to be maintained or more less, so as to reduce the unit cost of the circuit. For corresponding with the development of the high technology industry in the future, there is only one method to achieve this objective, that is, the area occupied by the devices shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have been shrunk to the deep sub-micron range. As the semiconductor device continuously shrinks to deep sub-micron region, some problems are incurred due to the process of scaling down.
There are many types of memories in the VLSI arena. Recently, magnetoresistive random access memory (MRAM) cells suitable for fabrication using current integrated circuit manufacturing processes have been developed for use as non-volatile storage elements. Magnetoresistive random access memory (MRAM) is based on the integration of Silicon CMOS with magnetic memory elements. Magnetoresistive random access memory (MRAM) is nonvolatile and has unlimited read and write endurance. Unlike DRAM, magnetic memory cells that store information as the orientation of magnetization of a ferromagnetic region can hold stored information for long periods of time, and are thus nonvolatile. Certain types of magnetic memory cells that use the magnetic state to alter the electrical resistance of the materials near the ferromagnetic region are collectively known as magnetoresistive (MR) memory cells. An array of magnetic memory cells is often called magnetic RAM or MRAM.
The two most viable magnetoresistive random access memory (MRAM) technologies are the pseudo spin valve (PSV) and the magnetic tunnel junction (MTJ) approaches. Recent advances in giant magnetoresistance (GMR) and magnetic tunnel junction (MTJ) materials give magnetoresistive random access memory the potential for high speed, low operating voltage, and high density. The two kinds of Current-In-Plane (CIP) giant magnetoresistance structures we considered are the spin valve and the pseudo spin valve (PSV). In the spin valve memory element, one of the magnetic layers is pinned while the other layer is free to change polarization, this free layer stores the information based on the direction of magnetic polarization with respect to the pinned layer. In this architectire, the resistance of the GMR storage element is compared with a reference cell to determine the state of the memory.
The pseudo spin valve structure consists of two magnetic layers of different thickness with Cu as an interlayer. The different thickness magnetic layers have different switching fields due to the shape anisotropy at submicron dimensions. The magnetic moments of the two magnetic layers can be predominantly anti-parallel or parallel, making the resistance of the film high or low respectively. A typical PSV memory cell stores information in the two possible polarization states of the thick magnetic layer. The bit is read non-destructively by applying a sense current together with a negative and then a positive digit current. The digit current magnitude is chosen such that the magnetic field generated by the digit current and the sense current combined is enough to switch the thin magnetic layer, but not enough to switch the thick magnetic layer.
The magnetoresistive random access memory array of conventional magnetoresistive memory cells is shown in FIG. 1A. The array includes a set of electrically conductive traces that function as parallel word lines 110A, 110B, and 110C in a horizontal plane, and a set of electrically conductive traces that function as parallel bit lines 120A, 120B, and 120C in another horizontal plane. The bit lines are oriented in a different direction, preferably at right angles to the word lines, so that the two sets of lines intersect when viewed from above, as shown in FIG. 1B. A memory cell, such as typical memory cell 130 shown in detail in FIG. 1C, is located at each crossing point of the word lines 110A, 110B, and 110C and bit lines 120A, 120B, and 120C in the intersection region vertically spaced between the lines. The memory cell 130 is arranged in a vertical stack that includes a pseudo spin valve (PSV) 140. The pseudo spin valve (PSV) 140 comprises a vertical stack of a pinned layer 150 having a non-variational direction of magnetization, a free layer 160 having a variational direction of magnetization and an interlayer 170 between the pinned layer 150 and the free layer 160.
During operation of the array, non-uniform magnetization at both ends and at trapped vortices, provides additional torque to facilitate the reversal process, therefore, the switching field is lowered. In the PSV type of memory, magnetization orientations of both the soft and hard layers needs to be reversed for read and write operation, respectively. For read the operation, the amplifier is first auto-zeroed, then the sense current is applied to the stack of active and reference bits while a negative digit current is applied to the active memory bit. The sense surrents remain on while the digit current is switched to the positive direction and the output of the amplifier is strobed. The bit information is determined by detecting the change in signal magnitude between the active bit cell and the reference cell.
Nevertheless, some of the issues result from this traditional structure. The traditional pseudo spin valve MRAM consists of orthogonal bit line and word line, as shown in FIG. 1B. In write mode, the thick magnetic layer is polarization between the induce field by bit line and word line. Therefore, it is necessary that a larger magnetic field is induced to form magnetoresistance, that is, there is a smaller magnetoresistance ratio (delta R) in the conventional pseudo spin valve MRAM. Furthermore, the higher writing current is also required. Accordingly, only field align to bit lines strip can make a strong magnetoresistance.
In accordance with the above description, a new and improved method for forming the cell of the magnetoresistive random access memory is therefore necessary, so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a method is provided for fabricating the magnetoresistive random access memory with the magnetic tunnel junction that substantially overcomes drawbacks of above mentioned problems arised from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for fabricating the magnetoresistive random access memory. This invention can form a novel array of the magnetoresistive random access memory to substitute for conventional structure, so as to obtain a good magnetiresistance performance. Hence, the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
Another object of the present invention is to provide a method for forming a pseudo spin valve (PSV) of the magnetoresistive random access memory. The present invention can form a word line strip that is located on the pseudo spin valve cell to parallel the bit line, so as to induce a larger magnetic field to form magnetoresistance, that is, there is a larger magnetoresistance ratio (delta R) in the present invention. Therefore, the low writing current is required in this invention. Accordingly, this invention can provide a magnetoresistive random access memory that has a good magnetiresistance performance to increase yield and quality of the process and, hence, decrease cost. Therefore, the present invention can correspond to economic effect.
In accordance with the present invention, a new method for forming a magnetoresistive random access memory is disclosed. The array includes: a plurality of pseudo spin valve (PSV) cells having a vertical stack that consists of a pinned layer, a interlayer and a free layer; a plurality of electrically conductive traces that function as parallel bit lines in a horizontal plane, wherein a plurality of bit lines are straight lines and located under the pinned layers of a plurality of pseudo spin valve (PSV) cells; a plurality of electrically conductive traces that function as parallel word lines in another horizontal plane, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with a direction of one of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the free layers of the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines to increase the magnetresistance ratio.